Ken Austin of Pilkington Microelectronics Ltd (PMel), Cheshire, UK, has designed the Dynamically Programmable Logic Device (DPLD), a gate array whose 10,000 physical gates’ mode of operation and layout of interconnections can be changed on the fly by software. This allows the chip to emulate virtually any logic circuit, while able to be partitioned to perform several different tasks simultaneously. The basis of the DPLD is a cell containing two circuits in a master-slave relationship.
Each of the circuits can be configured as a NAND gate, a register or a latch. PMel will make a specially designed CAD software package available with the chip, which it will license to semiconductor manufacturers. The chip can be produced by any CMOS process, making chip size and performance dependent on the capabilities of the semiconductor maker. Plessey Semiconductors Ltd has already licensed the DPLD for redesign as an ASIC cell it calls an electronically reprogrammable array (ERA) that should be available in February 1990.
An infinite number of gates on one chip is how Ken Austin of Pilkington Microelectronics Ltd. (PMeL), Cheshire, U.K., describes his latest uncommitted logic architecture. In reality, the device he designed has just 10,000 physical gates, but how the gates operate and the layout of interconnections among them can be changed on the fly by software. As a result, the chip can emulate virtually any logic circuit.
Further, it can be partitioned to perform several different tasks at once. One of those tasks can even be to reprogram and reconfigure parts of the chip itself. Either the whole chip or just a small section of it can be altered, and when only a small section is reconfigured, the rest of the chip can remain in operation. Austin says that the ability to partition and reprogram small sections of the chip can remain in operation. Austin says that the ability to partition and reprogram small sections of the chip while its still running is what distinguishes the Dynamically Programmable Logic Device (DPLD) from other PLDs. It also substantiates his claim that it can appear to contain an infinite number of gates.
Austin expects the DPLD to wind up in a broad range of applications, from systems that operate in inaccessible or remote locations–like satellites, where it’s impractical to physically make repairs or updates–to artificial-intelligence machines. He expects most users to first apply it to prototyping conventional ASIC devices, using the chip as a way to verify–or change–their designs, because it allows for continuous revision and updating during design and operation.
The basic element of the DPLD is a cell containing two circuits that can each be configured as a 2-input NAND gate, a register, or a latch. One of the gate circuits is defined as a master, the other as a slave. The master acts as a storage register or as a routing switch to determine how the slave gate interconnects with surrounding cells.
A series of predefined tracks on the chip “visit” each cell location, and among them allow for the definition of a hierarchy of routes. The arrangement of possible connections is similar to a telephone network, in which local links connect users to switches, which in turn are connected to other switches, and all are held together with a backbone of long-distance trunk interconnections.
The basic level of connection is what Austin calls a local interconnection. It makes it possible to connect about 30 or 40 adjacent gates, configuring them into a Boolean function. Other tracks define near connections between groups of locally interconnected cells, and finally, long distance global buses carry instructions and data to all parts of the chip (see the figure).
Each interconnection can be turned on or off using a configuration data file. As a result, the actual layout of the connections among cells varies depending on the function implemented at any given time. This variation in cell arrangements occurs in a manner that’s analogous to brain cells, says Austin.
Several methods are available for holding the controlling software. The simplest is to have the DPLD read configuration data directly from an external ROM, with the DPLD supplying the necessary addressing and control signals. This technique is useful for bootstrapping the device to an initial configuration. More flexibility can be achieved, though, by connecting an external counter to generate ROM addresses.
A more sophisticated method is to assign the job of configuration control to an external microprocessor, which selects the start address for a configuration held in ROM. Subsequent selections can implement any new functions or subfunctions as conditions and applications demand.
One interesting approach that Austin describes is to use the DPLD to change itself on-the-fly. For example, a portion of the chip could be configured on startup as an RS-232-C serial interface, which could then load the program data used to change other sections of the chip for specific applications. Yet another option would be to copy initial data configuration files from ROM into RAM. Then the application could modify itself as it receives data from a process being controlled.
Writing the software could be a chore, but Austin feels he has that problem covered. PMeL will have a specially designed CAD software package available. The software will take designers from capturing a schematic through to generating device-configuration data.
The software will be compatible with standard, high-level ASIC development languages, such as VHDL and Edith-2, according to Austin, and will allow simulation that verifies functionality and timing. Using the CAD package, designers will be able to build a library of software macros that can control the DPLD as a standalone chip, or as a megacell on a semicustom device.
PMeL’s parent company, Pilkington Group plc, St. Helens, Cheshire, U.K., while the world’s largest manufacturer of glass, doesn’t plan to make the silicon wafers. As a result, Austin is negotiating with about six international semiconductor companies who want to license the DPLD. He says that the chip can be made with any CMOS process, so chip size and performance will depend on the capabilities of the semiconductor makers.
So far, only one licensee has come forward: Plessey Semiconductors Ltd., Swindon, U.K., says that it intends to adapt the DPLD design as an ASIC cell that it calls an electronically reprogrammable array (ERA). Doug Dunn, the company’s managing director, sees it as “reusable silicon” and says that he will have it ready for sale around February. Built with Plessey’s 1.2-[micrometer] CMOS process, it should clock at 40 to 50 MHz, allowing reconfiguration to be carried out in about 1 ms.