Monthly Archives: October 2015

Resonant technology will spur power-supply design developments

Power supplies for the 1990s will require a new type of technology to become faster and smaller like the VLSI devices they support. A new power conversion concept, resonant technology has twin goals of increasing the power density of supplies and improving performance by operating at higher frequencies than current pulse-width modulation (PWM) supplies can handle.

The trend is also away from large centralized power supplies to distributed supplies designed as modular or board-mounted types. Board-mounted supplies will need to have the same low profile as ICs, necessitating improvements in component technology,

For most of the 1970s and 80s, switching power-supply design was based mainly on pulse-width modulation (PWM) circuits. But the 1990s will require a new type of technology. Because VLSI advances make electronic systems faster and smaller, future power supplies must follow suit.

VLSI technology shrinks everything except the demand for power. Over the past five years, a new power-conversion idea called resonant technology was under development in private companies and universities. Its aim is smaller and more efficient power supplies than what’s possible with PWM methods. In the long run, perhaps by the end of this decade, resonant technology and new component and circuit fabrication techniques could reduce certain types of power supplies to commodity products, much like ICs.

All resonant designs share common goals. First is to increase the power density of supplies. A second goal is to improve performance by operating at higher frequencies than is possible under PWM technology. With PWM techniques, 100-200 kHz is about the upper frequency limit. Resonant converters will operate at several MHz and above. A commercial 1-MHz resonant converter is now available.

The major trend is the move away from large centralized supplies to distributed supplies. Distributed supplies are more suitable for the smaller, faster systems resulting from the rapid advancement of VLSI technology. They’re designed as either modular supplies or board-mounted types. Increasingly decentralized supplies will be built with resonant technology.

Resonant technology and distributed power aren’t new ideas, but rather ideas whose time has come because we’re now gaining the technology to implement them. In addition to work at the Virginia Power Electronics Center at Virginia Polytechnic Institute and State University, MIT, AT&T, Bell Laboratories, General Electric, and Unisys are working on resonant converters.

Whereas conventional PWM supplies for computer systems have power densities of 1 or 2 [W/in..sup.3.], experimental resonant technologies are at least an order of magnitude higher. A design target at GE and at VPI’s Center is 50 [W/in..sup.3] intially, and 100 [W/in..sup.3] before the end of the decade. Bell Labs has demonstrated a resonant supply that can deliver 50 W and runs at 20 MHz. But most 50-W output, [50-W/in..sup.3] power converters operate from 2 to 4 MHz. Some of these types of supplies will be practical by the early 1990s.

Much of the impetus for developing high-density, 50-W supplies comes from the military. VHSIC requirements call for compact distributed supplies that mount directly on a logic board, deliver up to 50 W of 5-V power, with superior transient response to power logic that can be running at 100 MHz and greater. These converters must have a power density of 50 [W/in..sup.3] and operate at several MHz. The long-term objective–towards the end of the decade–is to build supplies in chip form and mount them on pc boards.

It should be no surprise that units with power densities of 50 [W/in..sup.3] must be highly efficient to reduce the amount of head produced. A 1-MHz resonant converter should be able to operate at 90% efficiency, considerably higher than the 80% figure of today’s PWM supplies. It’s almost an axiom in the design of high-frequency resonant supplies that you don’t have a technology until you can deal with the heat.

In addition to high power density, the coming generation of board-mounted supplies will have to have extremely low profiles, much like ICs. This means that improvements in component technology are necessary to flatten out the package. Magnetic elements in particular are receiving lots of attention in an attempt to reduce their size. A thin magnetic plate or substrate can have windings printed on it, and then be covered with a low-profile core to make a transformer. Multilayer pc-board techniques are already being applied to inductors and transformers. Capacitor technology is also advancing. It’s now possible to integrate many capacitors on one chip in a dual-in-line package.

Another reason to reduce magnetics to an IC-like technology is to take most of the labor out of the manufacturing process. If a transformer or inductor can be built like an IC, the process can be automated. In fact, this is the ultimate goal; manufacture a power supply just like you make an IC, and reduce it to a commodity product.


IC packaging must undergo a facelift to meet user needs

Chip technology will continue to drive packaging technology in the 1990s. The development of multichip modules will be one of the most significant changes in packaging in the next decade. Changes in chip technology including increased I/O leads on a single chip, increased mils per chip side, higher clock rates and faster signal-edge rates will contribute to the push toward multichip modules.

These modules could be built by semiconductor houses, by end users, or by third-party vendors, and all three modes are currently in process. Use of multichip modules will impact board and end-equipment manufacturers by reducing the number of interconnection levels, connectors, cables and sockets, and increasing the thermal management requirements of devices.

Chip technology has been the driving force behind packaging technology for a long time. Increases in a chip size, input/output pin counts, power dissipation, and speed have continually put new pressure on package developers to keep pace. This pressure will continue to grow in the future.

We have computer houses, for example, telling us that they can no longer afford signal delays that go out of a package, through a trace on a board, and back into another package. When it’s technologically and economically practical to integrate the functions onto one chip, this is the preferable route. Otherwise, the best alternative is to put the discrete chips into the same package.

There’s also concern by some customers about stresses that occur on large chips as they’re mounted in a package. For these reasons, I see the development of multichip modules to be one of the biggest changes in packaging during the next decade.

Increasing the I/O on a given chip to over a thousand leads is one of the things that will drive us into a multichip module–getting the I/O on a chip-to-chip level rather than a coming-to-the-outside-world level. Multichip modules are going to become increasingly important in performance for the systems user.

But who will produce these multichip modules, which will be largely custom or semicustom? A semiconductor house could make the module and sell it to end users, or users could buy chips and make the module themselves. Or end users could hire a third party to produce the module.

Currently, all three cases are happening. A few highly upward-integrated companies (for example, some Japanese companies and IBM) are already making modules. As subsystems shrink from pc boards to multichip modules, pc-board houses will follow that market. Moreover, because semiconductor houses can make the silicon and can interconnect chips at very fine levels, I think they’re going to be much more involved in the module business.

When the interconnection is driven back inside the package, it’s done at a level that the semiconductor house is accustomed to operating with. We’re accustomed to operating with wire bonding and tape-automated bonding (TAB), and with very fine leads and lines on a wafer. So there are a number of those pieces of technology that we’re very well equipped to handle.

Use of multichip modules will affect pc-board and/or end-equipment manufacturers in several ways. The number of interconnection levels that they have in a system is likely to decrease. They may have fewer connectors, cables, and sockets. However, use of these modules could require additional thermal management, because now we’re putting a lot more power into a more confined area. Packages dissipating up to 90 W will significantly affect the thermal aspect of their system.

By driving interconnections inside the package, you can partition the system to reduce the I/O count of the multichip module. We’ve already heard from some customers who have partitioned their system, reducing the number of I/O pins for the module to less than that used by one of the chips in the module.

Some major changes in chip technology are expected by the mid-90s: Chips will go from 380 mils to around 800 mils on a side. The maximum number of I/O leads will go from about 360 to about 1250. High-power chips that handle 30 W will triple that number. Clock rates will go from 30 MHz to 300 MHz, and signal-edge rates from the 600-ps range to 300 ps. All of these modifications will place big demands on package design, which will lead to the widespread use of multichip modules.

To increase the I/O while keeping the size of the package to a minimum, leads must get closer together. The standard pitch of 100 mils will soon go to 50 mils, and by the mid-90s, it could drop to 30 mils.

There will be an increase in lead arrays, either pin-grid or pad-grid, for surface mounting. The pad-grid array carrier’s spacing is currently as low as 50 mils, and will fall to 30 mils in the future.

At 30 mils, techniques must be developed to solder pad arrays. The proprietary technique that we’re presently using at 50 mils may not work as well at 30 mils. If it does, it’s going to take an additional degree of sophistication. Routing into these fine spaces will also require additional levels in the pc boards. But with surface-mounting, these levels would be connected with vias, rather than through-holes, which require much more area.