Accurate circuit simulation is necessary to get the most speed from submicron chip technology. This is also true for NCR Corp’s newest cell library which include submicron-feature devices that fall and rise 40 percent quicker than larger-feature devices. Accurate model techniques are needed to simulate the gate delays of the new Application-specific integrated circuits. The new VS700 line of cells are also 40 percent denser than NCR’s VS1500 cell library. Designers can simulate gate delays caused by rise and fall times down to 0.1 ns with the precise modeling technology.
Accurate circuit simulation is essential to pulling the highest possible speed from submicron chip technology. This is no less true for the latest cell library from NCR Corp., Fort Collins, Colo., which boasts submicron-feature devices that have much faster rise and fall times than their large-feature counterparts. And because gate-delay times vary with the rise and fall time, precise model technology is needed to accurately simulate the gate delays of these new ASICs.
Specifically, NCR’s new VS700 family of cells are 40% faster and denser than the company’s VS1500 cell library. These increases promise small, fast, and powerful end products. The submicron process produces features that are 0.95 [micrometer] drawn and have a 0.7-[micrometer] effective-channel length.
Simulation becomes difficult with submicron technology because second-order effects in a large-feature process assume first-order proportions at the submicron level. With this library, workstation models calculate each cell’s delay time as a function of rise and fall time and load capacitance. Accounting for load capacitance is a feature that makes the library especially valuable for improving critical-path performance.
With the precise modeling technology, designers can simulate gate delays caused by rise and fall times down to 0.1 ns (see the figure). In contrast, its competitors model delays from 1- to 1.5-ns edge times–a significant difference for submicron chips.
Lightly loaded critical paths have fast rise and fall times, and precise models accurately represent the faster delay times that result. Models are accurate enough to unmask circuit race conditions, giving designers a chance to correct them.
Another helpful feature of the new cell family’s design system is its set of high-level macros and compilers. Memory compilers, for example, are so flexible that designers can select word width as well the number of words. For example, designers can configure a RAM compiler to an exact bit width, and not have to settle for predefined blocks that may be larger and consume more die area than needed.
Customized symbols and models for simulation are automatically generated from the designer’s workstation input; there’s a faster time to market and no waiting for the vendor to configure high-level functions. And post-layout as well as prelayout routing capacities can be simulated. As a result, chip real-estate is assigned only for the amount of memory actually needed.