Category : Electrical and electronics industries

“Infinite” programmable gate array makes incremental changes on the fly

Ken Austin of Pilkington Microelectronics Ltd (PMel), Cheshire, UK, has designed the Dynamically Programmable Logic Device (DPLD), a gate array whose 10,000 physical gates’ mode of operation and layout of interconnections can be changed on the fly by software. This allows the chip to emulate virtually any logic circuit, while able to be partitioned to perform several different tasks simultaneously. The basis of the DPLD is a cell containing two circuits in a master-slave relationship.

Each of the circuits can be configured as a NAND gate, a register or a latch. PMel will make a specially designed CAD software package available with the chip, which it will license to semiconductor manufacturers. The chip can be produced by any CMOS process, making chip size and performance dependent on the capabilities of the semiconductor maker. Plessey Semiconductors Ltd has already licensed the DPLD for redesign as an ASIC cell it calls an electronically reprogrammable array (ERA) that should be available in February 1990.

An infinite number of gates on one chip is how Ken Austin of Pilkington Microelectronics Ltd. (PMeL), Cheshire, U.K., describes his latest uncommitted logic architecture. In reality, the device he designed has just 10,000 physical gates, but how the gates operate and the layout of interconnections among them can be changed on the fly by software. As a result, the chip can emulate virtually any logic circuit.

Further, it can be partitioned to perform several different tasks at once. One of those tasks can even be to reprogram and reconfigure parts of the chip itself. Either the whole chip or just a small section of it can be altered, and when only a small section is reconfigured, the rest of the chip can remain in operation. Austin says that the ability to partition and reprogram small sections of the chip can remain in operation. Austin says that the ability to partition and reprogram small sections of the chip while its still running is what distinguishes the Dynamically Programmable Logic Device (DPLD) from other PLDs. It also substantiates his claim that it can appear to contain an infinite number of gates.

Austin expects the DPLD to wind up in a broad range of applications, from systems that operate in inaccessible or remote locations–like satellites, where it’s impractical to physically make repairs or updates–to artificial-intelligence machines. He expects most users to first apply it to prototyping conventional ASIC devices, using the chip as a way to verify–or change–their designs, because it allows for continuous revision and updating during design and operation.

The basic element of the DPLD is a cell containing two circuits that can each be configured as a 2-input NAND gate, a register, or a latch. One of the gate circuits is defined as a master, the other as a slave. The master acts as a storage register or as a routing switch to determine how the slave gate interconnects with surrounding cells.

A series of predefined tracks on the chip “visit” each cell location, and among them allow for the definition of a hierarchy of routes. The arrangement of possible connections is similar to a telephone network, in which local links connect users to switches, which in turn are connected to other switches, and all are held together with a backbone of long-distance trunk interconnections.

The basic level of connection is what Austin calls a local interconnection. It makes it possible to connect about 30 or 40 adjacent gates, configuring them into a Boolean function. Other tracks define near connections between groups of locally interconnected cells, and finally, long distance global buses carry instructions and data to all parts of the chip (see the figure).

Each interconnection can be turned on or off using a configuration data file. As a result, the actual layout of the connections among cells varies depending on the function implemented at any given time. This variation in cell arrangements occurs in a manner that’s analogous to brain cells, says Austin.

Several methods are available for holding the controlling software. The simplest is to have the DPLD read configuration data directly from an external ROM, with the DPLD supplying the necessary addressing and control signals. This technique is useful for bootstrapping the device to an initial configuration. More flexibility can be achieved, though, by connecting an external counter to generate ROM addresses.

A more sophisticated method is to assign the job of configuration control to an external microprocessor, which selects the start address for a configuration held in ROM. Subsequent selections can implement any new functions or subfunctions as conditions and applications demand.

One interesting approach that Austin describes is to use the DPLD to change itself on-the-fly. For example, a portion of the chip could be configured on startup as an RS-232-C serial interface, which could then load the program data used to change other sections of the chip for specific applications. Yet another option would be to copy initial data configuration files from ROM into RAM. Then the application could modify itself as it receives data from a process being controlled.

Writing the software could be a chore, but Austin feels he has that problem covered. PMeL will have a specially designed CAD software package available. The software will take designers from capturing a schematic through to generating device-configuration data.

The software will be compatible with standard, high-level ASIC development languages, such as VHDL and Edith-2, according to Austin, and will allow simulation that verifies functionality and timing. Using the CAD package, designers will be able to build a library of software macros that can control the DPLD as a standalone chip, or as a megacell on a semicustom device.

PMeL’s parent company, Pilkington Group plc, St. Helens, Cheshire, U.K., while the world’s largest manufacturer of glass, doesn’t plan to make the silicon wafers. As a result, Austin is negotiating with about six international semiconductor companies who want to license the DPLD. He says that the chip can be made with any CMOS process, so chip size and performance will depend on the capabilities of the semiconductor makers.

So far, only one licensee has come forward: Plessey Semiconductors Ltd., Swindon, U.K., says that it intends to adapt the DPLD design as an ASIC cell that it calls an electronically reprogrammable array (ERA). Doug Dunn, the company’s managing director, sees it as “reusable silicon” and says that he will have it ready for sale around February. Built with Plessey’s 1.2-[micrometer] CMOS process, it should clock at 40 to 50 MHz, allowing reconfiguration to be carried out in about 1 ms.


Communication among processors sustains fast, massively parallel computer

Designers at Maspar Computer Corp in Sunnyvale, CA have developed two chips intended to break the communications bottleneck that often occurs in highly parallel computers. One chip serves to simplify and accelerate global interprocessor communications. The second chip carries 32 highly interconnected processing elements (PEs). A fully configured MasPar system can yield performance rates of 10,000 MIPS and 1,000 MFLOPS. Two independent communication schemes are built into the PE chips. A neighborhood mesh connects each PE to its eight nearest neighbors, while a multistage crossbar hierarchy allows each PE to connect to any other PE in the array. The 32 processors on each PE chip are formed from 500,000 transistors. RISC-style load-store architecture with local cache memory keeps each PE as small as possible.

Highly parallel computers employ hundreds, even thousands, of small processors to achieve astounding computational rates. Execution rates can reach billions of operations per second. At the same time, however, the interprocessor communication needed for sending commands and transferring data can become a bottleneck when so many processors run simultaneously.

To break that bottleneck, designers at MasPar Computer Corp., Sunnyvale, Calif., developed two custom chips: One simplifies and accelerates global interprocessor communications, and the other supplies 32 highly interconnected processing elements (PEs).

The MasPar system can harness from 1024 to 16,384 processor elements and, when fully configured, deliver 10,000 MIPS (millions instructions per second) and 1000 MFLOPS (million floating-point operations per second). The system employes a single-instruction-stream and multiple-data (SIMD) architecture manipulated by an array-control unit (ACU).

MasPar at NASA/GSFC

The ACU fetches and decodes instructions and issues control signals to all PEs. All PEs execute the same instruction stream, but each can also have local autonomy over execution, allowing for localized calculations.

To achieve the high bandwidth needed for thousands of PEs to communicate among themselves, MasPar designers built two independent communication schemes into the system. One is a neighborhood mesh, or X-net local interconnection that ties each PE to its eight nearest neighbors. The other is a multistage crossbar hierarchy that lets each PE connect to any other PE in the array. The X-net forms a 2D grid that wraps around East to West and North to South to form a torus-like pattern (see the figure below).

Within each PE chip are packed 500,000 transistors that form 32 processors interconnected in a 2d grid. Multiple PE chips are interconnected in the same way that processors are within a chip.

According to Jeff Kalb, MasPar Computer’s founder and president, each PE is kept as small as possible by using a RISC-style, load-store architecture with local cache memory for each PE.

What’s more, only four paths per PE are needed to communicate in eight directions. That’s because the X-shaped crossing points of the communication paths are three-state nodes that switch the data to one of two paths. All of the interprocessor X-net connections use bit-serial communications, so just 24 pins per PE chip are required for the X-net interface.

Some computational problems don’t map well onto an X-net topology, however, and require arbitrary interconnections among PEs. To tackle that problem, a team headed by Tom Blank, director of architecture and application development, designed the multiple custom router chips so they could form a multistage interconnection network, which is somewhat like a hierarchy of crossbar switches. Each router chip has 64 datapath inputs and 64 datapath outputs, and can switch any input to any output.

When a PE chip sends data to a router, it first multiplexes the output from 16 PEs onto one outgoing router path and one incoming router path. Router paths are bit serial, so only four pins are needed on each PE chip to multiplex 32 PEs.

Once a connection is established, the router’s bidirectional data paths send or fetch data. In a 16,384-PE system, up to 1024 simultaneous connections can be established, thus giving an aggregate data rate of over 1 Gbyte/s.

The multistage interconnection network is well matched to SIMD architectures because all connections occur with the same timing and sequence in each PE. The common timing and sequencing greatly simplifies the logic compared to a hypercube-type architecture.

In a hypercube, different path lengths can cause messages to arrive at each PE at different times, raising hard-to-solve timing considerations. In contrast, the router network in MasPar’s system keeps the message delays identical, eliminating timing problems. In addition, the router network tracks parity for all data and addresses to ensure highly reliable transfers–a critical task when thousands of processors are involved. Furthermore, each router chip includes diagnostic logic that detects open wires in the network.


Wanted: world-class designers

Any consideration of the direction of design engineering over the next ten years must start with a look back; to know where we are going, we must know where we have been. Science and technology were once regarded as the solution to all problems.

Events such as Hiroshima and Nagasaki, Three Mile Island and Chernobyl have led people not merely to doubt this, but in many cases to believe that technology is actually the cause of all our problems. The truth of the matter is that technology is an integral part of everyday life. Changes wrought by technology are more extreme and happening more quickly every day. Such massive change calls for a special class of design engineer. To cope with the rapid changes, today’s design engineer must make innovation a standard. Further, to be successful, the design engineer must be able to read the market, to find a need and fill it. And, above all, the new breed of design engineer must be a team player, for teamwork will be essential to meet the challenges of the next decade and beyond.

The last decade of the century has begun. Instead of addressing a specific technology, which is the norm for this column, we take a longer, broader focus to consider the new demands that designers will face in the coming years. It’s unwise, though, to speculate about the next decade–facing the next millennium as we are–without looking back. In making predictions, perspective is everything–to know where you’re going, you must know where you are. It also helps to know how you got there. Such perspective is as important for design engineering as it is for hiking on trails or navigating the seas.

Where have we come from? Much of our professional heritage flows from the philosophy of Positivism, a nineteenth century discourse of thought that tended to put science and technology on a pedestal. In that mode of popular thinking, all problems were subordinate to the power of reason, the scientific process, and the application of technology. In Positivism, science and technology were held as the saviors of humanity. Religion was snubbed as a problem solver; God and mysticism were out. Scientists became the new priests; their laboratories, the new shrines. With the splitting of the atom, however, that thinking began to change.

From the moment we exploded the atom bomb, doubts have crept into our certainty about the absolute benefit of science. Consider the U.S. nuclear-energy industry after Three Mile Island and Chernobyl, a shambles with almost no public support; or the way that sophisticated medical technology has backfired into soaring health costs; or how the environment–our very source of life–faces irreversible damage under the strain of what’s called progress. Worst of all, consider the fact that, as satellites and the Space Shuttle circle the sky, forty-thousand people–most of them children–die each day from chronic hunger and malnutrition. And in New York City, one of the largest cities in the world’s richest nation, 40% of the children live in poverty. Clearly technology isn’t the solution to all our problems. Indeed, some would say–albeit naively–it’s the source.

At the same time, we can’t live without technology. It is solidly a part of our everyday life. More than that, as each day passes, technology is transforming our world, linking our lives as never before. Indeed, technology is one of the driving forces creating a global economy. Telecommunications and computers are changing business on a scale not seen since–and likely greater than–the Industrial Revolution.

The changes are radical and happening fast. Such changes, and the demands they bring, call for a new breed of design engineer: a world-class designer. Innovation, once an occasional part of the design process, is now a necessary ingredient for success. The increasing pace of innovation has shrunk the design time and life cycle of our industry’s output. As a result, to create tomorrow’s successful products, designers must develop the art of innovation, not as a sometimes things, but as an everyday practice. Companies that don’t build the best technology into their products, as well as into their business practices, will be surpassed by those that do.

Tomorrow’s successful designers will also need to be students of the marketplace. They must help find what is missing in the market and produce it. Technical competence alone won’t be enough. The force of emerging and unexpected opportunities in a global arena coupled with increasingly complex technology means one thing at least: Teamwork will be essential. No individual, acting alone, will be able to decide the what, when, and how of a successful product. Only an innovative and skilled team, with each member–worldclass designers included–familiar with the others’ discipline, can even hope to ride the wave of tomorrow.