Tag : Chip technology

IC packaging must undergo a facelift to meet user needs

Chip technology will continue to drive packaging technology in the 1990s. The development of multichip modules will be one of the most significant changes in packaging in the next decade. Changes in chip technology including increased I/O leads on a single chip, increased mils per chip side, higher clock rates and faster signal-edge rates will contribute to the push toward multichip modules.

These modules could be built by semiconductor houses, by end users, or by third-party vendors, and all three modes are currently in process. Use of multichip modules will impact board and end-equipment manufacturers by reducing the number of interconnection levels, connectors, cables and sockets, and increasing the thermal management requirements of devices.

Chip technology has been the driving force behind packaging technology for a long time. Increases in a chip size, input/output pin counts, power dissipation, and speed have continually put new pressure on package developers to keep pace. This pressure will continue to grow in the future.

We have computer houses, for example, telling us that they can no longer afford signal delays that go out of a package, through a trace on a board, and back into another package. When it’s technologically and economically practical to integrate the functions onto one chip, this is the preferable route. Otherwise, the best alternative is to put the discrete chips into the same package.

There’s also concern by some customers about stresses that occur on large chips as they’re mounted in a package. For these reasons, I see the development of multichip modules to be one of the biggest changes in packaging during the next decade.

Increasing the I/O on a given chip to over a thousand leads is one of the things that will drive us into a multichip module–getting the I/O on a chip-to-chip level rather than a coming-to-the-outside-world level. Multichip modules are going to become increasingly important in performance for the systems user.

But who will produce these multichip modules, which will be largely custom or semicustom? A semiconductor house could make the module and sell it to end users, or users could buy chips and make the module themselves. Or end users could hire a third party to produce the module.

Currently, all three cases are happening. A few highly upward-integrated companies (for example, some Japanese companies and IBM) are already making modules. As subsystems shrink from pc boards to multichip modules, pc-board houses will follow that market. Moreover, because semiconductor houses can make the silicon and can interconnect chips at very fine levels, I think they’re going to be much more involved in the module business.

When the interconnection is driven back inside the package, it’s done at a level that the semiconductor house is accustomed to operating with. We’re accustomed to operating with wire bonding and tape-automated bonding (TAB), and with very fine leads and lines on a wafer. So there are a number of those pieces of technology that we’re very well equipped to handle.

Use of multichip modules will affect pc-board and/or end-equipment manufacturers in several ways. The number of interconnection levels that they have in a system is likely to decrease. They may have fewer connectors, cables, and sockets. However, use of these modules could require additional thermal management, because now we’re putting a lot more power into a more confined area. Packages dissipating up to 90 W will significantly affect the thermal aspect of their system.

By driving interconnections inside the package, you can partition the system to reduce the I/O count of the multichip module. We’ve already heard from some customers who have partitioned their system, reducing the number of I/O pins for the module to less than that used by one of the chips in the module.

Some major changes in chip technology are expected by the mid-90s: Chips will go from 380 mils to around 800 mils on a side. The maximum number of I/O leads will go from about 360 to about 1250. High-power chips that handle 30 W will triple that number. Clock rates will go from 30 MHz to 300 MHz, and signal-edge rates from the 600-ps range to 300 ps. All of these modifications will place big demands on package design, which will lead to the widespread use of multichip modules.

To increase the I/O while keeping the size of the package to a minimum, leads must get closer together. The standard pitch of 100 mils will soon go to 50 mils, and by the mid-90s, it could drop to 30 mils.

There will be an increase in lead arrays, either pin-grid or pad-grid, for surface mounting. The pad-grid array carrier’s spacing is currently as low as 50 mils, and will fall to 30 mils in the future.

At 30 mils, techniques must be developed to solder pad arrays. The proprietary technique that we’re presently using at 50 mils may not work as well at 30 mils. If it does, it’s going to take an additional degree of sophistication. Routing into these fine spaces will also require additional levels in the pc boards. But with surface-mounting, these levels would be connected with vias, rather than through-holes, which require much more area.