VHDL simulator supports 100% of the DOD standard
Silicon Compiler Systems (SCS) introduces Explorer VHDLsim, an IEEE 1076-1987 VDHL standard-compliant simulator. VHDLsim is integrated into SCS’s Explorer Lsim mixed-signal, multilevel simulation environment, giving engineers transparent access to resources including the Mach 1000 accelerator and Spice simulation. VHDLsim provides both the M and VDHL languages for engineers who choose to use analog and digital behavioral modeling. Mixing analog and digital modeling in the same simulation enables the inclusion of VHDL in mixed-signal designs. Explorer VHDLsim will be available in second quarter 1990 at a cost of $30,000 if purchased as an option to Explorer Lsim. A standalone version will be priced at $42,000.
Because of its heavy backing by the U.S. government and the IEEE, VHDL should make its mark on the CAE industry during the next few years. That’s made clear by the flurry of VHDL activity among simulation vendors. The latest to announce VHDL simulation support is Silicon Compiler Systems (SCS).
SCS supports the IEEE’s 1076-1987 VHDL standard with Explorer VHDLsim, a simulator that’s integrated into the company’s Explorer Lsim mixed-signal, multilevel simulation environment. The new simulator’s most important feature is its 100% support of the language, including behavioral, structural, and data-flow levels. Moreover, users can simulate VHDL models from any source.
Another key feature is the simulator’s meshing with the larger Lsim environment. That means, for example, users can have transparent access to resources such as the Mach 1000 accelerator and Spice simulation. Because the Explorer Lsim environment can simulate from the architectural level all the way down to the Spice level, the top-down design process need not stop at the gate level. Structural VHDL models may be simulated at the gate-, switch-, and circuit-levels in Explorer VHDLsim. This is possible because users won’t need to change simulation environments to get their designs in shape.
In cases where designers choose to use analog and digital behavioral modeling, the simulator gives them both the M and VHDL languages, respectively. M is a superset of the C language and is used for both digital and analog behavioral modeling. Because M is a full programming language, proprietary simulation algorithms may also be added. Translations from M into VHDL will be supplied where possible for those users with extensive libraries written in M and who need to document these models in VHDL.
By mixing analog and digital models in the same simulation, designers can include VHDL in mixed-signal designs as well as in pure digital designs. In addition, with VHDLsim there’s no performance penalty for using the VHDL language.
For accurate timing simulation, users will be able to run mixed-signal simulations using device-level representations where that level of accuracy is needed, and VHDL behavioral or gate-level models everywhere else. This includes mixed-signal simulation using HSpice and VHDL by means of the Lsim/HSpice interface that SCS has developed with MetaSoftware Inc., Campbell, Calif.
SCS’s Explorer Lsim environment comes with an interactive, source-level symbolic debugger that will be used for both VHDL models and models written in the M hardware-description language (see the figure). Other benefits of the tight integration with SCS’s design-automation products include schematic capture, synthesis, and other front- and back-end tools. “Integration is something that SCS can bring to the party that other standalone VHDL suppliers can’t,” claims James Griffeth, director of product marketing for SCS.
As if 100% support of the standard wasn’t enough to make VHDLsim stand out, it’s also distinguished by its performance. The simulator uses SCS’s direct-compilation technology, which is much faster than simulators using interpretive-language technology. This is because the VHDL code is compiled directly into C rather than a proprietary hardware-description language.
As a result of its alliance with CAD Language Systems Inc. (CLSI), Rockville, Md., VHDLsim includes CLSI’s VHDL Tool Integration Platform (VTIP), a set of front-end design-capture tools. As far as users are concerned, a simple pushbutton operation compiles source code into an executable circuit model. First, the code comes in through the CLSI VHDL parser, which parses it into the intermediate format. After that, the code is automatically accessed and optimized by VHDLsim, which compiles it directly into C. The resulting C object files are then further optimized by the C compilers native to the designer’s workstation.
Explorer VHDLsim supports the ability to do incremental compiling and dynamic loading. During a given simulation, designers may wish to modify one of the behavioral models in the hierarchy. An incremental compilation recompiles just the model that was changed, which is much faster than recompiling or reinterpreting the entire environment. Those recompiled models can be dynamically loaded without having to leave the simulator, which saves a great deal of time. That’s because users avoid simulation start-up time as well as the overall compile time or reinterpretation time.
According to Griffeth, SCS achieved 100% support of the VHDL language so quickly because of its four years of active participation in the IEEE’s VHDL standardization movement. As a result, the company had access to many of the leading-edge VHDL concepts as they took shape and heeded their architectural implications.